New Place and Route Algorithms for Wire Length Improvement With Concern to Critical Paths

3D Circuits are one of the most promising technologies for reducing wire lengths [1] and improving circuit power [2] and timing [3] for future high performance designs. On a 3D VLSI Circuit, tiers of active area are stacked, providing higher integration density, shrinking the distances between the cells and reducing wire lengths as a consequence. In order to take full benefit of the technology, new algorithms on the CAD field must be provided to handle 3D arrangement of circuit elements while considering new issues caused by the 3D integration. Today, the research in this field is still on the early years. Consider the 3D placement problem, for instance. The richness and variety of techniques that led to significant advances on 2D circuit placement over the decades will be able to deliver similar maturity to the 3D placement field. This thesis targets the wire length improvement of VLSI circuit considering critical elements of a circuit. It considers the problem from two different perspectives: placement and routing. On placement, it explores methods to perform placement of 3D circuits considering issues related to vertical interconnects (3D-Vias). A very significant volume of new methods and contributions are presented in the text and fully validated in a tool called Z-Place (section II). On routing, a new flexible algorithm called AMAZE is proposed (section III), combining existing and new methods that are very effective to produce short wire length and low delay to critical elements.